A lower-part alternate-bit truncated approximate adder is proposed in this work. The approximate LSB part of the adder is truncated with an alternate-bit pattern based on the computed carry to the accurate MSB part. The error parameters such as mean error distance and error rate and the circuit parameters like power consumption, delay, and resource utilization for an FPGA implementation were evaluated for the proposed approximate adder design. The efficacy of the approximate adder circuit was tested by deploying it to an edge detection application. To benchmark the performance of the proposed adder in edge detection, peak signal-to-noise ratio (PSNR) metric was used. The approximate adder proposed in this work detected edges with the same PSNR value as the LOA approximate adder but with a drop in power consumption of 4.92%. Moreover, the simulation proved that an accurate ripple carry adder dissipates 15.09% more power in comparison to the proposed approximate adder.