The rapid development of emerging intelligent applications leads to a surge in computational demands and memory capacity requirements. Compute-in-memory (CIM) is a promising paradigm to alleviate the data movement bottleneck of emerging intelligent applications. SRAM-based CIM technology is employed to enhance the performance of general-purpose processors (e.g., CPU) by reusing on-chip memory (e.g. Cache) for computational tasks. In recent SRAM-based CIM works, peripheral compute circuits, e.g., adder trees, are introduced to improve system performance, as SRAM cells are hard to support arithmetic operations efficiently. However, the excessive peripheral circuit with a large area overhead degrades the memory density, which breaks the balance of computation and memory. To improve the computing capability and memory capability simultaneously of digital-based CIM (DCIM), we propose SSC, an SRAM-based silence computing CIM design, which leverages logic-in-memory operations and peripheral circuits to achieve parallel computing within the SRAM array. We propose \(8^+\) T (8T, 9T, and 11T) SRAM bitcells to support majority-of-three (MAJ3), COPY, and NOT logic, which is used to achieve a 3:2 compressor. Furthermore, a silence computing design, facilitated by a local connection between SRAM cells, is proposed to improve system parallelism, which supports parallel logic-in-memory operations and memory access. Our experiment results show that SSC achieves 3.7 \(\times \) memory density improvement compared to prior DCIMs normalized to 12nm. Additionally, the SWaP ( \(TOPS/W \times Kb/mm^2\) ) figure-of-merit emphasizes the importance of memory density and energy efficiency, showing that this work achieves a higher SWaP of 119.89, which is 1.84 \(\times \) more than prior DCIMs normalized to 12 nm.