Silicon MOSFETs have been the cornerstone of the microelectronics industry. Following Moore’s Law, the number of transistors on a chip has doubled approximately every two years, driven by the shrinking size of MOSFETs. This consistent device scaling has led to significant improvements in both density and performance, with dimensions now reaching the nanometer regime. However, further scaling of conventional MOSFETs becomes challenging due to short-channel effects (SCE), where the narrowing separation between source and drain exacerbates leakage currents. As a result, transistors struggle to function as clean on–off switches, as current leaks through even when the gate voltage is removed. The reduction in threshold voltage (Vth) further increases the subthreshold leakage current, complicating the complete shutdown of the device. To address the challenges associated with scaling conventional MOSFETs, this study investigates the impact of gate length and channel geometry on leakage current by comparing single-gate MOSFETs with multigate structures. Simulations were conducted using NanoHUB's ABACUS and NanoTCAD ViDES tools to analyze various performance metrics, including leakage current (Ioff), drive current (Ion), Ion/Ioff ratio, and threshold voltage (Vth). The comparison focuses on how these metrics vary with different gate lengths and channel geometries. In particular, the study examines the performance of GAA silicon nanowire MOSFETs, exploring their electrostatic control and potential advantages in ultra-scaled technology nodes. This analysis is aimed at understanding the effectiveness of innovative channel geometries and multigate designs in overcoming the limitations posed by traditional MOSFET structures as device dimensions continue to shrink.