This paper aims to present a new VLSI architecture for image processing applications where the use of DA method makes it memory efficient. The key goal of the proposed architecture is to avoid problems inherent in conventional techniques based on heavy memory usage, while providing more efficient resource utilization. Distributed Arithmetic works with distribution of arithmetic operations over the memory elements, which leads to a lesser memory utilization and improved performance. When incorporated in the context of image processing as done by our architecture, the technique aims at enhancing the utilization of available resources to improve the overall performance and energy efficiency. In the proposed design methodology, memory efficiency in VLSI architectures is highlighted, especially in the context of image processing. In this work, we have shown that the proposed approach is theoretically and experimentally valid and can achieve a performance competitive with or even higher than existing architectures while using much less memory. In this spirit, the present work offers a state-of-the-art VLSI architecture of image processing based on the principles of Distributed Arithmetic as a viable solution for attaining efficient computation while minimizing associated memory overheads. This work forms part of benefits in achieving power and area efficient architectures for image processing applications to enable better solutions in VLSI domain.