Neural-symbolic systems (NSSs), which are typically cyber-physical systems integrated with artificial intelligence modules, have received much attention in both academic and industrial fields. However, thorough verification (such as model checking) of such systems in general leads to prohibitively high costs due to the scale of the state space, and this makes it barely accomplishable within desired time-span. Consequently, light-weight verification techniques are introduced to deal with such cases, e.g., runtime verification (RV, for short). In this paper, we investigate an RV framework for NSSs against signal temporal logic (STL) properties. To guarantee that the on-line monitoring could be accomplished in time, we utilize Euler-prediction to sample the system under scrutiny at discrete time-steps. Our framework supports both qualitative and quantitative on-line monitoring of STL specifications, and thus it terminates whenever a property is satisfied and/or violated by a finite prefix of the trajectory, and it can also provide the bounds of the quantitative satisfaction/violation w.r.t. the remaining execution. Notably, for the so-called piece-wise linear NSSs against affine STL formulas, our approach is exact. On top of it, a prototype tool is implemented, and is experimentally evaluated. The results demonstrate the feasibility of the presented runtime verification approach.

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Runtime Verification of Neural-Symbolic Systems

  • Shaojun Deng,
  • Wanwei Liu,
  • Miaomiao Zhang

摘要

Neural-symbolic systems (NSSs), which are typically cyber-physical systems integrated with artificial intelligence modules, have received much attention in both academic and industrial fields. However, thorough verification (such as model checking) of such systems in general leads to prohibitively high costs due to the scale of the state space, and this makes it barely accomplishable within desired time-span. Consequently, light-weight verification techniques are introduced to deal with such cases, e.g., runtime verification (RV, for short). In this paper, we investigate an RV framework for NSSs against signal temporal logic (STL) properties. To guarantee that the on-line monitoring could be accomplished in time, we utilize Euler-prediction to sample the system under scrutiny at discrete time-steps. Our framework supports both qualitative and quantitative on-line monitoring of STL specifications, and thus it terminates whenever a property is satisfied and/or violated by a finite prefix of the trajectory, and it can also provide the bounds of the quantitative satisfaction/violation w.r.t. the remaining execution. Notably, for the so-called piece-wise linear NSSs against affine STL formulas, our approach is exact. On top of it, a prototype tool is implemented, and is experimentally evaluated. The results demonstrate the feasibility of the presented runtime verification approach.