In recent years, with the rise of deep learning theory and the development of computer equipment capabilities, convolutional neural networks (CNNs) have demonstrated a strong potential for application in a number of fields such as computer vision and natural language processing. Although CNNs have completely surpassed human capabilities in a number of fields, such as image recognition, their huge computational demand is still a focus of attention in the scientific community. Traditional CPUs and GPUs have problems in terms of efficiency and power consumption. While FPGAs have the advantages of highly parallel computing, flexible programmability, low power consumption, and low latency, designing CNN-based FPGA hardware accelerators has become an important research direction today. This paper will analyze the previous research results in the direction of optimizing the efficiency of CNN, focusing on the study of the convolutional layer of convolutional computation, and take advantage of the important pipeline structure in FPGAs to accelerate the convolutional computation of the convolutional layer of convolutional neural network by designing the FPGA pipeline multiplier and the pipeline tree adder using the Verilog language and experimenting in the simulation platform, so as to achieve optimization of CNNs.