This paper delves into the hardware implementation and simulation verification of the Threshold Offset Minimum Sum Algorithm (TOMSA) for Low-Density Parity-Check (LDPC) decoding. LDPC is a linear block code and widely used in many communication fields, which is preferred for its great performance and low difficulty to be implemented on hardware. TOMSA is a modified Min-Sum Algorithm (MSA) proposed by Homayoon Hatami. It has better performance than MSA especially in high SNR condition. The Verilog program developed in this paper has been meticulously designed to meet the specific requirements of LDPC decoding. The simulation results confirm that the Verilog program successfully achieves the intended objectives, demonstrating the practicality and efficacy of the TOMSA algorithm in a hardware context. The paper provides a detailed account of the design process, the functionality of the TOMSA algorithm, and the simulation outcomes, which validate the program’s performance and its potential for integration into real-world applications.