To enhance the operational efficiency of the Kalman filter, this study leverages the parallel computing capabilities of field-programmable gate array (FPGA) to process the state matrix and related data updates within the Kalman filter algorithm. The Verilog language is employed to redefine the operations and processing procedures of the Kalman filter, while incorporating the design concept of a finite state machine to enhance the overall program structure of the filter. For this project, software environments such as MATLAB and Modelsim 2020.4 SE were utilized to simulate and test the algorithmic program. Initially, MATLAB was employed to validate the Kalman filter algorithm, followed by algorithm optimization to enhance its applicability based on issues identified during simulation verification. Finally, the FPGA design of the filter was implemented using Verilog, and Modelsim was employed to conduct simulation tests, thereby confirming the feasibility of the proposed approach.