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Floating-point number operations are widely used in scientific computing, engineering simulations, financial modeling, and data analysis because of its ability of quick processing while maintaining the accuracy. Compared with integer and fixed-point representations, they enable more accuracy and manipulation of real numbers in various computational tasks, ranging from numerical analysis to machine learning algorithms. However, among the arithmetic operations, the most complex ones are the addition/subtraction operations compared to multiplication/division operations due to the unique way of processing data in binary systems, which differs a lot from human calculations. In this paper, a floating-number calculator is programmed using finite-state machine (FSM) triggered by clock period through Verilog hardware description language (VHDL) and implemented on FPGA. The Verilog code is in accord with IEEE 754 standard, and the standard will be illustrated visually. The states of the finite-state machine along with the conditions required to transmogrify are also to be discussed in this article, using pictures to help readers fully comprehend the code. Also, simulations will be provided in this paper and analyzed. Future applications as well as possible adaptations will also be discussed due to the deficiencies of the existing calculator.

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Single-Precision Floating-Point Adder Based on IEEE 754 Standard Through Verilog

  • 会议论文

  • 发表日期：

    2025年

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  • Cong Guo,
  • Zhouchi Jia,
  • Yechen Lin,
  • Haozhe Yang

摘要

Floating-point number operations are widely used in scientific computing, engineering simulations, financial modeling, and data analysis because of its ability of quick processing while maintaining the accuracy. Compared with integer and fixed-point representations, they enable more accuracy and manipulation of real numbers in various computational tasks, ranging from numerical analysis to machine learning algorithms. However, among the arithmetic operations, the most complex ones are the addition/subtraction operations compared to multiplication/division operations due to the unique way of processing data in binary systems, which differs a lot from human calculations. In this paper, a floating-number calculator is programmed using finite-state machine (FSM) triggered by clock period through Verilog hardware description language (VHDL) and implemented on FPGA. The Verilog code is in accord with IEEE 754 standard, and the standard will be illustrated visually. The states of the finite-state machine along with the conditions required to transmogrify are also to be discussed in this article, using pictures to help readers fully comprehend the code. Also, simulations will be provided in this paper and analyzed. Future applications as well as possible adaptations will also be discussed due to the deficiencies of the existing calculator.