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To address the challenges of complex network structures and high computational demands in deep learning-based low-level vision algorithms, which hinder real-time inference on power-constrained heterogeneous platforms, we propose a lightweight dual-task (Super-Resolution, SR, and Low-Light Enhancement, LLE) vision network optimization framework for FPGA deployment: SL-SYENet. Compared to SYENet, SL-SYENet significantly reduces computational load and parameter count while maintaining accuracy for LLE and SR tasks. Through a three-stage approach—task-decoupled training, dynamic sharing and merging, and mixed-precision quantization—the framework fuses two decoupled task models, achieving real-time performance with reduced resource consumption. Evaluated on the FMQL100TAI platform, SL-SYENet achieves a PSNR of 22.10 dB for LLE and 29.79 dB for SR, with a power consumption of 12.9 W and an inference time of 55 ms.

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Multi-task Low-Level Vision Network for FPGA Deployment: SL-SYENet Joint Optimization Framework

  • 会议论文

  • 发表日期：

    2026年

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  • Shenao Li,
  • Yongjiang Xue,
  • Fei Qiao,
  • Qingzeng Song

摘要

To address the challenges of complex network structures and high computational demands in deep learning-based low-level vision algorithms, which hinder real-time inference on power-constrained heterogeneous platforms, we propose a lightweight dual-task (Super-Resolution, SR, and Low-Light Enhancement, LLE) vision network optimization framework for FPGA deployment: SL-SYENet. Compared to SYENet, SL-SYENet significantly reduces computational load and parameter count while maintaining accuracy for LLE and SR tasks. Through a three-stage approach—task-decoupled training, dynamic sharing and merging, and mixed-precision quantization—the framework fuses two decoupled task models, achieving real-time performance with reduced resource consumption. Evaluated on the FMQL100TAI platform, SL-SYENet achieves a PSNR of 22.10 dB for LLE and 29.79 dB for SR, with a power consumption of 12.9 W and an inference time of 55 ms.