Network-on-Chip (NoC) is widely used for on-chip communication in System-on-Chip designs. Application mapping, a key design step, aims to improve NoC performance. As design demands become more sophisticated and scales expand, existing application mapping optimization methods lack multi-objective optimization capabilities to support flexible design and struggle to ensure both effectiveness and efficiency in large-scale implementations. In this paper, we propose a multi-objective application mapping optimization strategy for large-scale NoC designs, which employs a MILP-based method to obtain mappings that meet diverse requirements of high throughput, low latency and low power consumption. Additionally, the strategy integrates a pruning method using heuristic partitioning and pre-mapping techniques to reduce the search space efficiently while preserving solution quality, thereby balancing computational efficiency with solution effectiveness. Experimental results show that the mappings generated by this strategy outperform both randomly generated mappings and those generated by advanced methods under both low-communication-cost and high-throughput scenarios. Moreover, the strategy balances efficiency and effectiveness in large-scale designs, demonstrating excellent scalability.