With the rapid advancement of information technologies and the increasing demand for secure and efficient data processing, symmetric encryption algorithms have become essential to ensuring digital communication security. SM4, a standardized 128-bit block cipher, is widely adopted in security-critical fields such as finance, embedded systems, and telecommunications. However, traditional software implementations often fail to meet the real-time performance and scalability demands of high-throughput environments. This paper proposes a high-performance SM4 encryption/decryption accelerator based on FPGA, utilizing a hardware-software co-design approach and fine-grained parallelism. The architecture integrates a modular SM4 core with a processor via an AXI+APB bus interface, enabling streamlined communication and flexible control. Key components include specialized submodules for key expansion and a 32-round iterative encryption submodules, optimized for low latency and efficient resource utilization. The system is implemented on a lightweight FPGA platform and validated through functional simulation and hardware-in-the-loop testing. Experimental results show a per-round encryption latency of only 0.572 microseconds, significantly outperforming traditional software approaches. This design presents a scalable and energy-efficient solution suitable for secure, real-time applications in embedded environments.