Multi-scalar multiplication (MSM) is the core computational bottleneck in zero-knowledge proof systems, and traditional implementations face severe performance limitations in large-scale computations. This paper proposes a systematic MSM vectorization optimization framework targeting the vector computing characteristics of digital signal processors (DSPs). The framework exhibits excellent generality, adapting to platforms with different SIMD widths and various elliptic curves. First, we design a vectorized big-number arithmetic library based on mask operations, eliminating the impact of conditional branches on SIMD execution efficiency through assembly-level optimizations tailored to DSP architectural features. Second, we propose a three-layer reduction algorithm that fully exploits DSP’s hierarchical memory architecture, achieving efficient parallel accumulation through pipelining mechanisms while considering transmission overhead. Finally, we design a pipelined mechanism that overlaps computation and data transfer to maximize hardware resource utilization. Experimental results on the FT-M7032 heterogeneous processor demonstrate that our scheme achieves significant performance improvements of 13.36–65.46 \(\times \) compared to the libff baseline implementation across various MSM scales. This scheme provides an efficient solution for practical deployment of zero-knowledge proofs and offers important theoretical foundations and practical guidance for cryptographic algorithm optimization on heterogeneous computing platforms.