Modern Post-Quantum Cryptography (PQC) is represented by the latest standardized Kyber (ML-KEM) and Dilithium (ML-DSA) algorithms from NIST. Nevertheless, significant on-chip data movement overhead inherent in PQC hardware critically constrains computational efficiency. To address these issues, we propose an application-specific instruction set architecture (ISA) extension optimized for PQC systems termed PQIns. This architecture achieves enhanced performance-resource efficiency through a configurable four-stage pipeline (fetch-decode-execute-feedback) employing distinct instruction classes: configuration directives, execution operations, and flow-control commands. Moreover, this framework integrates specialized accelerators comprising an expanded 8-way parallel processing for rejection sampling and an \(\eta \) -adaptive parallel Centered Binomial Distribution (CBD) sampler, a high-throughput 320-bit Keccak engine, and a unified modular arithmetic units and a customized data flow finite state machine (FSM) for number theoretic transform (NTT). Finally, system-level optimizations further incorporate execution-phase reordering with pipeline staggering, alongside memory coalescing and register, file enhancements to decouple computation from bandwidth constraints. Evaluated on Xilinx KCU105 platform, PQIns used 15K/30K LUTs, 11K/18K FFs,10/14 DSPs and 14/20 BRAMs respectively in ML-KEM/DSA, at 200 MHz clock frequency. Compared with the state-of-the-art other works, the performance improves \(10\%\) ( \(\pm 4\%\) ) and \(5\%\) ( \(\pm 4\%\) ). As a novel ISA extension natively supporting both ML-KEM/DSA parameter sets, this work establishes an extensible hardware-software co-design framework for lattice-based cryptosystems, bridging quantum-resistant algorithmic complexity and hardware efficiency.