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In the latest Transport Layer Security (TLS) v1.3 protocol, ChaCha20 and the Advanced Encryption Standard (AES) are the only supported encryption algorithms. ChaCha20, a variant of Salsa20, is widely recognized for its simplicity, robust security, and compatibility. Given the sensitive nature of much of the data processed on supercomputers remotely, efficient encryption is paramount. However, encrypting large-scale data can be time-consuming. To address this challenge, we propose a parallel implementation of the ChaCha20 algorithm on the MT-3000 heterogeneous multi-zone processor. By leveraging its unique architectural features, we employ various optimization techniques, including multilevel parallel strategies for heterogeneous multi-zone architecture, Direct Memory Access (DMA) for efficient data transmission, and Single-Instruction Multiple Data (SIMD) for parallel data processing within the acceleration core. Experimental results demonstrate the effectiveness of our parallel scheme, achieving a throughput of up to 168.11 GB/s on a single MT-3000 processor, and finally scaling to 512 acceleration clusters with good scalability.

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A Parallel Implementation of ChaCha20 on MT-3000 Heterogeneous Multi-zone Processor

  • 会议论文

  • 发表日期：

    2026年

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  • Yongtao Luo,
  • Jie Liu,
  • Tun Li,
  • Chunye Gong

摘要

In the latest Transport Layer Security (TLS) v1.3 protocol, ChaCha20 and the Advanced Encryption Standard (AES) are the only supported encryption algorithms. ChaCha20, a variant of Salsa20, is widely recognized for its simplicity, robust security, and compatibility. Given the sensitive nature of much of the data processed on supercomputers remotely, efficient encryption is paramount. However, encrypting large-scale data can be time-consuming. To address this challenge, we propose a parallel implementation of the ChaCha20 algorithm on the MT-3000 heterogeneous multi-zone processor. By leveraging its unique architectural features, we employ various optimization techniques, including multilevel parallel strategies for heterogeneous multi-zone architecture, Direct Memory Access (DMA) for efficient data transmission, and Single-Instruction Multiple Data (SIMD) for parallel data processing within the acceleration core. Experimental results demonstrate the effectiveness of our parallel scheme, achieving a throughput of up to 168.11 GB/s on a single MT-3000 processor, and finally scaling to 512 acceleration clusters with good scalability.