Automatic vectorization in traditional compilers is often unreliable, as the required high-level program structure is lost in low-level intermediate representations (IRs). This forces compilers to rely on fragile analyses to rediscover opportunities for SIMD execution, leading to unpredictable performance. This paper presents a novel, robust vectorization framework built upon the Multi-Level Intermediate Representation (MLIR) that avoids this pitfall by leveraging high-level semantics preserved in the linalg dialect. This paper introduces a tiling-aware optimization strategy, embodied in a three-phase, model-driven methodology. This strategy is guided by an analytical cost model that, by leveraging hardware-specific performance parameters, determines the lowest-cost vectorization plan that synergistically combines data locality from tiling with robust, masked vectorization to ensure high performance. Experimental evaluations demonstrate the framework’s effectiveness. On compute-intensive kernels like GEMM, our method achieves speedups of over 18x for data sizes that fit within the L3 cache, significantly outperforming industry compilers like GCC and Clang. Notably, on large-scale Conv2D, the synergistic combination of tiling and vectorization delivers a speedup of over 30x, validating our tiling-aware vectorization method.