As lattice-based cryptography emerges as the leading post-quantum candidate, efficient implementation of the Number Theoretic Transform (NTT) becomes critical for CRYSTALS-Kyber’s hardware deployment. This paper addresses the urgent need for resource-constrained environments by presenting an efficient area-performance balanced NTT accelerator design. This paper proposed a compact modular reduction unit that requires only 52 LUTs and 1 DSP corrected from a previous design, an optimized storage scheme with coordinated PWM module, and a four-way parallel NTT architecture based on radix-2 butterfly units achieves the most efficient hardware resource utilization. Implemented on Virtex-7 FPGA, our accelerator achieves a 0.76 µs NTT latency while maintaining minimal resource consumption. The architecture demonstrates significant improvements in area-time efficiency over existing solutions, establishing an optimal hardware foundation for Kyber deployment in edge devices and IoT systems.