As an upgraded version of ZUC-128, ZUC-256 serves as a stream cipher algorithm in high-speed communication (e.g. 5G mobile communication) for data confidentiality and integrity protection. However, the multi-input modulo ( \(2^{31} - 1\) ) addition used in its linear feedback shift register forms a performance bottleneck. Existing approaches typically decompose the multi-input modulo ( \(2^{31} - 1\) ) addition into a series of two-input modular addition and insert pipeline registers to shorten critical path delay. Although this method helps to raise the throughputs, it significantly increases register cost. To address this issue, an area-efficiency Compression Array Modulo ( \(2^{31} - 1\) ) Adder (CAMA) is proposed. The CAMA can achieve high speed comparable to the traditional two-input modulo ( \(2^{31} - 1\) ) adder without requiring additional pipeline registers. Moreover, by combining bit-width partitioning with parallel addition optimization, the 31-bit carry chain in the CAMA can be reduced to 16 bits. Furthermore, we apply the bit-width partitioning strategy to the finite state machine module of ZUC-256, effectively balancing delays across pipeline stages. To evaluate the performance of our proposal, we conduct experiments on three platforms including Spartan-6, Virtex-5, and Virtex-7 FPGA. On the Spartan-6 platform, the proposed design achieves a maximum throughput of 4103 Mbps, improving 18.0% on the Throughput-to-Area Ratio (TAR) over existing studies. On the Virtex-5 platform, the maximum throughput further increases to 5334 Mbps, accompanied by a 48.64% reduction in area overhead (i.e. 97.5% improvement in TAR). On the Virtex-7 platform, the proposal reaches a throughput of 7111 Mbps with only 359 slices cost, fully demonstrating its exceptional resource efficiency and strong potential for practical engineering applications.