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Bottom-gate n-type Gallium Nitride (GaN) thin-film transistor (TFT) was designed and simulated using a dual gate dielectric stack of Si3N4/SiO2. The device structure consists of an Al bottom gate, a 70 nm GaN active channel, Al/Au bilayer source-drain contacts, and a SiO2/Si3N4 passivation layer. The simulated TFTs exhibit promising electrical characteristics, including a threshold voltage (Vth) of 0.29 V, and a subthreshold swing (SS) of 74 mV/dec. The low threshold voltage and steep subthreshold swing indicate strong gate controllability and reduced interface trap effects at the GaN/dielectric interface. These results demonstrate that the proposed GaN TFT structure offers excellent potential for low-power and high-speed thin-film electronics.

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Design and TCAD Simulation of Bottom-Gate GaN Thin-Film Transistor with Dual Gate Dielectric Stack

  • 会议论文

  • 发表日期：

    2026年

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  • Mohith Reddy Gundre

摘要

Bottom-gate n-type Gallium Nitride (GaN) thin-film transistor (TFT) was designed and simulated using a dual gate dielectric stack of Si3N4/SiO2. The device structure consists of an Al bottom gate, a 70 nm GaN active channel, Al/Au bilayer source-drain contacts, and a SiO2/Si3N4 passivation layer. The simulated TFTs exhibit promising electrical characteristics, including a threshold voltage (Vth) of 0.29 V, and a subthreshold swing (SS) of 74 mV/dec. The low threshold voltage and steep subthreshold swing indicate strong gate controllability and reduced interface trap effects at the GaN/dielectric interface. These results demonstrate that the proposed GaN TFT structure offers excellent potential for low-power and high-speed thin-film electronics.