Dielectric Stack Engineering for Low Power and Reliable ZnO Thin Film Transistors
摘要
This work presents a TCAD based study of ZnO thin film transistors (TFTs) with bilayer gate dielectrics and SiO2/Si3N4 passivation. In the simulated structures, the dielectric layer, D1 acts as as an interface passivation oxide, while the D2 dielectric layer provides the primary gate capacitance. Combinations of SiO2, Al2O3, HfO2, ZrO2, and TiO2 were explored in different interface-bulk configurations. Key electrical parameters including threshold voltage (Vth), subthreshold slope (SS), and Ion/Ioff ratio were extracted. Results indicate that while high-k bulk oxides improve drive current, but also increase leakage, making the interfacial dielectric critical for stability. The Al2O3/SiO2 stack acheived the best performance, with a steep SS 0.077 V/dec, ultra low-off current of 10−15A, and On/Off current ratio of 108. These findings highlight the role of dielectric stack engineering in enabling low-voltage, reliable ZnO TFTs suitable for transparent and flexible electronics.