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The modern System-on-Chip (SoC) architectures, including heterogeneous sensors, have enabled autonomous vehicles, robotics, and Internet of Things (IoT) devices, which demand real-time, high-fidelity sensor fusion to produce valuable information based on numerous diverse streams of data. Nonetheless, conventional architectures cannot meet these requirements because the latency and energy used to transfer data systemically between processing cores and memory are high, thereby limiting throughput and scalability in resource-aware embedded systems. It is in an attempt to address these issues that the paper is founded, and in the process, a new architecture of Memory-conscious Processing-in-Memory (PIM) is developed and uniquely designed to handle real-time sensor fusion in SoCs. Placing the fusion computation units directly into hierarchical memory configurations and structures, such as register files, SRAMs, and DRAM banks, in its design swiftly minimises the number of data transfers by exploiting data locality to advantage and reducing bottlenecks. Additionally, the architecture utilises dynamic precision arithmetic. It relies on dynamic accuracy enhancement of computations, which depends on the characteristics of sensor data and the demands of the fusion stage, thereby minimising power consumption without sacrificing quality fusion. It features an aggressive hardware planner that enhances sensor streams to ensure time sensitivity, enabling Quality of Service (quality of service) for real-time fusion pipelines. It has inbuilt security and wavering tolerance aims at safeguarding information when sensor inputs are noisy and there might be malfunctions. The results of energy savings achieved through absolute sensor data experimental tests related to the memory-aware PIM architecture demonstrate a 70% energy saving and a threefold reduction in fusion latency compared to the traditional SoC implementation, using a pair of independent processing cores. Additionally, the system maintains reasonable fusion accuracy due to its adaptive calculation algorithm. The findings suggest the potential of utilising the architecture as a scalable, energy-efficient, and high-performance solution for the next-generation embedded sensor fusion system, which will enable more intelligent, stronger, and more robust real-time applications.

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Memory-Aware Processing-in-Memory Architectures for Real-Time Sensor Fusion in SoC Platforms

  • 会议论文

  • 发表日期：

    2026年

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  • Hassan MuhamedAle,
  • Haeedir Mohameed

摘要

The modern System-on-Chip (SoC) architectures, including heterogeneous sensors, have enabled autonomous vehicles, robotics, and Internet of Things (IoT) devices, which demand real-time, high-fidelity sensor fusion to produce valuable information based on numerous diverse streams of data. Nonetheless, conventional architectures cannot meet these requirements because the latency and energy used to transfer data systemically between processing cores and memory are high, thereby limiting throughput and scalability in resource-aware embedded systems. It is in an attempt to address these issues that the paper is founded, and in the process, a new architecture of Memory-conscious Processing-in-Memory (PIM) is developed and uniquely designed to handle real-time sensor fusion in SoCs. Placing the fusion computation units directly into hierarchical memory configurations and structures, such as register files, SRAMs, and DRAM banks, in its design swiftly minimises the number of data transfers by exploiting data locality to advantage and reducing bottlenecks. Additionally, the architecture utilises dynamic precision arithmetic. It relies on dynamic accuracy enhancement of computations, which depends on the characteristics of sensor data and the demands of the fusion stage, thereby minimising power consumption without sacrificing quality fusion. It features an aggressive hardware planner that enhances sensor streams to ensure time sensitivity, enabling Quality of Service (quality of service) for real-time fusion pipelines. It has inbuilt security and wavering tolerance aims at safeguarding information when sensor inputs are noisy and there might be malfunctions. The results of energy savings achieved through absolute sensor data experimental tests related to the memory-aware PIM architecture demonstrate a 70% energy saving and a threefold reduction in fusion latency compared to the traditional SoC implementation, using a pair of independent processing cores. Additionally, the system maintains reasonable fusion accuracy due to its adaptive calculation algorithm. The findings suggest the potential of utilising the architecture as a scalable, energy-efficient, and high-performance solution for the next-generation embedded sensor fusion system, which will enable more intelligent, stronger, and more robust real-time applications.