The Reversible Multiplier is a computational apparatus employed for the purpose of multiplying two binary values through the utilization of reversible addressing. The significance of the development of a reversible multiplier arises from its extensive applicability in the realization of computer networks utilizing emerging technology. In the majority of multipliers that have been shown thus far, there is a unique separation between the partial product generators and the adders. This results in an augmentation of the quantity of blocks comprising the ultimate circuit. In the realm of reversible computing, it is imperative for circuits to incorporate ancilla inputs and garbage outputs. As the amount of blocks in a circuit increases, there is a corresponding increase in the quantity of inputs as well as outputs. The present work involves the creation of a column-wise structure for the multiplier, with the aim of decreasing the quantity of individual blocks comprising it. The expense associated with enlarging reversible circuits in modern devices is substantial. The quantity of blocks utilized in the framework proposed in this research for a reversible multiplier exhibits a notable reduction in comparison to preexisting designs. Additionally, the blocks in question are designed to limit the quantity of ancilla inputs and trash outputs. Hence, the suggested multiple criteria exhibit significantly lower values compared to those of the prior studies. In the suggested methodology, the multiplier is not built in two distinct stages; rather, every multiplier column is created as a cohesive block. Hence, the quantity of blocks comprising the circuit is equivalent to the quantity of columns in the multiplication process.