Cloud-based deep learning inference is often unsuitable for edge devices, where stringent constraints on power, compute resources, and latency must be met. To this end, we introduce LERIS, a RISC–V compatible system-on-chip (SoC) that integrates an accelerator specifically designed for real-time, resource-efficient, and low-power Artificial Intelligence (AI) inference. The accelerator features MAC trees using Wallace multipliers and carry-skip adders, a three-stage pipeline, and an on-chip memory architecture that minimizes both internal and external data transfers. Supporting convolutional neural networks (CNNs) and multilayer perceptrons (MLPs), the architecture achieves 14.1 \(\times \)  and 6.3 \(\times \) speedups on MNIST and ECG-heartbeat benchmarks, respectively, compared to a standalone soft processor (Original SoC) baseline, while preserving post-quantization accuracies of 96.80% and 94.45%. The LERIS achieves operation at a power consumption of just 0.625 W when running at 80 MHz on a Xilinx Artix-7 FPGA (Arty A7-100T board). This figure is merely 2.3 times greater than the power usage of the Original SoC. These advances yield a scalable, energy-conscious solution for low-latency and high-efficiency inference in real-time edge AI applications.