This paper presents on how we can replace the multipliers with basic operations like shifting and addition in the linear convolution method considering ease of implementation, making it ideal for low-power, resource constrained environments, such as embedded systems and software-based applications. We have implemented the concept of vertical and crosswise multiplication procedure, which is an ancient Vedic multiplication process, by replacing the multiplication property with shift and add operations. To enhance efficiency, we integrate this approach with a pipelined architecture that allows parallel data handling and partial product accumulation, resulting in a compact, low-power, and hardware-friendly design. The system supports fixed-size finite-length sequences and uses buffer registers to load input data in a streaming fashion. Simulation and synthesis are performed using Verilog HDL in Xilinx Vivado, and results demonstrate that the proposed design significantly reduces power consumption and hardware utilization compared to conventional parallel multiplier-based implementations. The approach proposed in this paper outperforms similar state-of the-art research work in terms of power consumption, as shown in comparative results. The performance analysis confirms that our technique provides a favorable trade-off between computational accuracy, speed, and resource efficiency, making it a strong candidate for real-time signal processing in portable and power-sensitive digital systems.