The use of approximate computing has grown significantly in a variety of error-tolerant situations where absolute correctness is not necessary. There are always many challenges being faced and few among them are design complexity where it increased when approximation techniques like truncation, simplification, or approximate adders and compressors are used, and finding a balance between allowable accuracy loss and gains in power, area, or speed is the second most challenge. In many of these applications, multiplication is essential since it is a basic arithmetic process. This paper investigates the construction of 8-bit multipliers that improve performance by utilising encoded summation of partial products and approximate 4:2 compressors. Further optimisation of the design is achieved by introducing unique approximate full adders and approximate 4:2 compressors from Ansari et al. (IEEE J Emerg Select Top Circ Syst 8:404–416, 2018), Yi et al. (Design of an energy-efficient approximate compressor for error-resilient multiplications. In: IEEE international conference on circuits and systems (ISCAS), 2019) to handle the summing of partial products in the less significant bit location. Through the utilisation of these methods, we successfully strike a compromise between precision and notable enhancements in crucial design parameters, specifically area, power, and delay. Using the Cadence Design Suite and a 45-nm standard cell library, we implemented RTL to GDSII (ASIC) of our approximate multiplier design and also the performance of all the designs are assessed using the same tool and the image merging application are also tested in MATLAB Software and they can be seen using in biomedical image merging used to improve the efficacy, precision, and quality of image-based analysis.