CRYSTALS-Kyber is one of the finalized algorithms in post-quantum cryptography standardization, designed to withstand quantum attacks. It is based on hard lattice-based mathematical problems, with polynomial multiplication being the primary performance bottleneck in lattice-based cryptographic (LBC) algorithms. These multipliers require modular arithmetic like modular adders, multipliers, and reductions. Polynomial multiplication is most time-consuming block while implementation of these cryptographic architecture and challenges designer to implement area-efficient yet simple architecture. This paper provides a concise area-delay performance analysis for the modular multiplier architectures. Experimental results show that the Russian Peasant multiplier with Improved Barrett reduction is 10% more area-efficient than the Karatsuba multiplier with Special Moduli but has 15% higher delay. Both designs serve as close alternatives. These multiplier architectures were implemented in Verilog and tested using the AXI-Lite interface via the PYNQ overlay method. All the designs are validated on Pynq-z2 platform where Russian Peasant is proved as best choice for modular multiplier than Karatsuba multiplier for CRYSTALS-Kyber cryptographic algorithms.

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FPGA-Based Implementation of Modular Multiplier for CRYSTALS-Kyber

  • Divya Vyas,
  • Abhijit Asati,
  • Gaurav Purohit

摘要

CRYSTALS-Kyber is one of the finalized algorithms in post-quantum cryptography standardization, designed to withstand quantum attacks. It is based on hard lattice-based mathematical problems, with polynomial multiplication being the primary performance bottleneck in lattice-based cryptographic (LBC) algorithms. These multipliers require modular arithmetic like modular adders, multipliers, and reductions. Polynomial multiplication is most time-consuming block while implementation of these cryptographic architecture and challenges designer to implement area-efficient yet simple architecture. This paper provides a concise area-delay performance analysis for the modular multiplier architectures. Experimental results show that the Russian Peasant multiplier with Improved Barrett reduction is 10% more area-efficient than the Karatsuba multiplier with Special Moduli but has 15% higher delay. Both designs serve as close alternatives. These multiplier architectures were implemented in Verilog and tested using the AXI-Lite interface via the PYNQ overlay method. All the designs are validated on Pynq-z2 platform where Russian Peasant is proved as best choice for modular multiplier than Karatsuba multiplier for CRYSTALS-Kyber cryptographic algorithms.