Binary Splitting Test Generation for a Pattern Matching Accelerator with In-Memory-Processing Architecture
摘要
Set Operating Processor (SOP) is a new type of device for accelerating pattern matching, consisting of a matrix of modules that integrate registers and logical operation capabilities, called pixels. The testing method for individual pixels in SOP has been clarified in our previous research; however, the testing method for multiple pixels has not yet been established. As pixel matrices scale up, testing the bridge faults caused by wiring shorts between pixels becomes challenging due to the number of potential faults increasing exponentially with the number of pixels. This paper proposes an optimized test generation method that uses a binary splitting approach to cover all possible bridge faults with minimal test patterns. By iteratively halving the verification pattern used for data matching, the method generates log(n) test patterns to test all single bridge faults in a matrix containing n pixels. Experiments on SOP matrices up to 4096 × 2160 demonstrate that the method significantly reduces required test patterns—from billions to just a few dozen—while maintaining 100% fault coverage. The proposed method enables the efficient realization of SOP tests between multiple pixels, which had not been established previously. This advancement also promotes the practical implementation of large-scale SOP devices.