This paper compares an in-depth review of various memory cell types and array designs. For quite some time, improving performance has revolved around focusing on memory. Researchers have explored various techniques and designs to enhance the performance of individual or multiple memory components. Among these, Bit cell design, integral to SRAM functionality Optimization of array configurations represents a relatively recent area of exploration. Numerous bit cells have been proposed in the literature part of this paper, and the number of transistors in a cell is the traditional way to classify cells. This paper summarizes the features and schematic drawings for various bit cells grouped according to the number of transistors. Consequently, this paper thoroughly analyses the various memory cells and array designs.