A Comparative Analysis of 9 T SRAM Array with Different Single Ended Sense Amplifiers for Optimal SRAM Read Performance at 32 nm Technology Node
摘要
Sense amplifiers are an extremely important part in the process of read operation and are vital for designing SRAM cells. Through this research study, the integration of a 9 T WARD SRAM cell with three distinct single-ended sense amplifiers: the Pulsed PMOS Sense Amplifier (PPSA), Switching NMOS Sensing Amplifier (SNSA), and Half Latch- Based Sense Amplifier (HLSA) has been conducted and analysed. Power, delay, and power delay product (PDP) were the metrics evaluated across a voltage range of 0.8–1.2 V to further analyse the performance characteristics of these configurations. The research revealed notable differences in power consumption, delay, and PDP, highlighting essential factors for selecting sense amplifiers in SRAM designs. The HLSA was found to have higher power consumption than PPSA but maintained relatively constant power across different voltages. On the other hand, PPSA was found out to exhibit significantly lower delay values compared to HLSA, with the delay remaining almost constant for PPSA and decreasing for HLSA as voltage increased. As a consequence of this, PPSA exhibited a significantly lower power delay product compared to HLSA, emphasizing its potential for efficient SRAM design across varying operating voltages.