A novel extended source dual gate tunnel field effect transistor (ESDGTFET) is suggested and studied with the use of Atlas TCAD simulation. To ensure its optimum efficiency, the dimensions of the suggested structure are optimized. We conduct a temperature study of the suggested structure, where the off-current (IOFF) increases and the subthreshold slope (SS) decreases with rise in temperature, since temperature change impacts the device performance. Further investigation is undertaken to examine the effect of temperature change on Analog/RF characteristics, including cut-off frequency (fT), transconductance (gm) and parasitic capacitances. The suggested structure is shown to be less influenced by temperature fluctuation at lower gate voltages and to achieve better characteristics at higher values of gate voltages as temperature rises.