Clocking is another critical step in VLSI chip design. Majority of the design blocks are sequential in nature and can’t work without a clock source and clock delivery structure in place. Most events which are synchronous in nature happen on clock edges. While implementing a clock tree in the design, we are faced with multiple challenges like clock synchronization, clock delay, clock skew and jitters. The following chapter discusses techniques used for clock optimizations and delay reduction of better performance. Various algorithms like performance analysis of nano-scaled FinFETs, Radiation hardened NMOS only Schmitt trigger-based latch design, a novel 4:2 compressor architecture for high performance application, clock skew reduction for peak current reduction is discussed in the chapter.