A Low-Power Chopper Amplifier with Offset Compensation DC Servo Loop
摘要
This paper presents a Capacitive Coupled Instrumentation Amplifier (CCIA) with ultra-low power consumption and low noise, specifically designed for wearable Electroencephalogram (EEG), Local field potential (LFP) and Action potential (AP) applications. The proposed CCIA architecture employs an Inverter-Based Folded-Cascode Amplifier (IBFCA) in the first amplification stage to enhance power supply noise rejection and extend bandwidth. The amplifier is optimized to handle DC electrode offsets of up to ±50 mV while maintaining high-quality EEG signal integrity. A DC Servo Loop (DSL) is utilized to eliminate DC offsets. The circuit is designed using a 0.18 µm CMOS process and operates with a total supply current of only 2.07 µA from a 1 V supply voltage. The amplifier achieves a Power Supply Rejection Ratio (PSRR) of 150 dB and a Common-Mode Rejection Ratio (CMRR) of up to 130 dB. With a total power consumption of 2.07 µW, the design is highly suitable for wearable EEG devices powered by coin-cell batteries. The Input-Referred Noise (IRN) is only 2.41 µV over the frequency range of 0.9 Hz to 10 kHz.