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To handle today's complicated challenges, it is critical to design a specific architecture for each application. MIMO (multiple-input multiple-output) systems are commonly regarded as the integral part of future wireless communication technology. The massive quantity of real-time computation necessary is a key barrier to its implementation. To meet this problem, efficient complexity reduction algorithms and approaches are being developed that are especially tuned to the needs of VLSI circuits. In terms of power consumption and space constraints, an efficient VLSI architecture is proposed based on these factors. Hardware platforms like FPGAs and GPUs provide flexibility to implement complex algorithms. In this paper, an optimized exhaustive search algorithm is proposed and implemented on FPGA with reduced power consumption and area utilization for MIMO baseband processing.

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Efficient VLSI Architecture for MIMO Communication Implemented on FPGA

  • 会议论文

  • 发表日期：

    2026年

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  • M. Thillai Rani,
  • M. Navin Kumar,
  • M. Jaishree,
  • K. P. Sai Pradeep

摘要

To handle today's complicated challenges, it is critical to design a specific architecture for each application. MIMO (multiple-input multiple-output) systems are commonly regarded as the integral part of future wireless communication technology. The massive quantity of real-time computation necessary is a key barrier to its implementation. To meet this problem, efficient complexity reduction algorithms and approaches are being developed that are especially tuned to the needs of VLSI circuits. In terms of power consumption and space constraints, an efficient VLSI architecture is proposed based on these factors. Hardware platforms like FPGAs and GPUs provide flexibility to implement complex algorithms. In this paper, an optimized exhaustive search algorithm is proposed and implemented on FPGA with reduced power consumption and area utilization for MIMO baseband processing.