Scholarlink

The optimization of digital circuits is crucial in modern technology; the performance of an electronic device is enhanced by optimizing the power and delay of the circuit. In this paper, an arithmetic and logic unit (ALU) is proposed using transistor-level design in CADENCE using different technologies and analyzed their performance. Using 45 nm technology library, the proposed design achieved a propagation delay of 13.29 ps, an operating frequency of 8.95 GHz, and power dissipation of 0.257 µW.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Delay and Power Analysis of ALU with 180, 90, and 45 nm Technologies

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Rahul Ganesh Karapothula,
  • J. Motheesh,
  • T. Deekshith,
  • M. Madhushankara,
  • Ribu Mathew

摘要

The optimization of digital circuits is crucial in modern technology; the performance of an electronic device is enhanced by optimizing the power and delay of the circuit. In this paper, an arithmetic and logic unit (ALU) is proposed using transistor-level design in CADENCE using different technologies and analyzed their performance. Using 45 nm technology library, the proposed design achieved a propagation delay of 13.29 ps, an operating frequency of 8.95 GHz, and power dissipation of 0.257 µW.