This proposal suggests significantly improving the safety, the security, and the reliability of drones via a novel design technique that combines fault tolerance (FT) design methodology, the use of Hierarchical Operations that employ a distributive version of Hierarchical Temporal Memory (HTM), and a novel set of design and testing tools. The system balances the need to guarantee no single point of failure and the requirement to operate at minimum resources such as area and power consumption. The system is designed to support a drone swarm, so, at the system level, a drone that loses a critical sensor, such as GPS, can retrieve the information from a neighbor drone. At the lower level of the hierarchy, an individual drone is controlled by a dedicated SoC that contains multiple RISC-V cores and a set of sensors. Each SoC contains an SMU (Security Management Unit), a small control unit that executes the top level of the distributed HTM algorithm and provides security services to the entire SoC. A set of dedicated sensors and targeted security counters are connected to the SMU; each sensor performs dedicated measurements and the lower level of the distributed HTM algorithm. The novel implementation of the algorithm is designed to consume minimum amount of power as long as the drone operates in a “normal” mode. Extra power is needed only if abnormal behavior is detected. The unique hierarchical implementation is designed to offer the best performance and power of the control system while providing a best-of-class recovery mechanism. Thus, it will enable an unstoppable system’s operation even under extreme (unknown) conditions, malfunction of any single component (or at least all components that were designed with redundancy in mind), or security attacks. Validating the correct operation of FT real-time systems requires the development of new simulation and testing tools. This proposal suggests extending our current Gazebo-based simulation environment to emulate system-wide failures and security attacks on drone swarms together with a unique FPGA-based Fault injection tool. The targets for such operations will be determined from existing reported CWEs and by using a set of new tools, we are developing that take advantage of “information flow tracking” (IFT). The end goal of our proposal is to develop and demonstrate via an FPGA-based system, a proof of concept of the proposed method and its supporting tools.