Dataflow accelerators leverage massive parallelism through customized architectural designs, making them highly efficient for tensor computations like matrix multiplications. However, designing dataflow accelerators is a complex task that requires seamless integration of software mapping and hardware optimization. Existing synthesis techniques often focus exclusively on either software or hardware optimizations, resulting in inefficiencies and extended development cycles. This paper proposes a unified synthesis framework that integrates software and hardware parts through a multi-level intermediate representation (IR). The framework progressively lowers dataflow representations into synthesizable hardware descriptions, enabling the rapid exploration of software mapping strategies and transparent hardware synthesis optimizations. The experimental results demonstrate a 14x improvement over CIRCT HLS by leveraging parallelism through software optimizations. The multi-level IR also facilitates efficient cross-level simulation to identify bugs and performance bottlenecks.