Scholarlink

In the domain of software development, testing is a critical phase that often dictates the reliability and performance of the final product. As software complexity grows, traditional testing methods become increasingly time-consuming and resource-intensive. This is where the confluence of configurable Single Instruction, Multiple Data (SIMD) architecture, and Field Programmable Gate Arrays (FPGAs) offers a groundbreaking solution. Using the adaptability of FPGAs and SIMD parallelism, software testing processes can be dramatically accelerated. This study proposes a framework for parallel software testing using SIMD architecture in FPGA. To minimize the testing time of a generated software product, the proposed solution utilized hardware employed for process execution. The prototype of the proposed system achieved promising speedup up to 115X using FPGA slow mode, and 81X on average over Windows-based testing method.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Leveraging Configurable SIMD Architecture in FPGA for Accelerated Software Testing

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Dheya Mustafa,
  • Issa Qandah,
  • Abdalrahman Alshannaq,
  • Ammar Zeidan,
  • Hassan Taqieddin,
  • Tamara Ghatasha

摘要

In the domain of software development, testing is a critical phase that often dictates the reliability and performance of the final product. As software complexity grows, traditional testing methods become increasingly time-consuming and resource-intensive. This is where the confluence of configurable Single Instruction, Multiple Data (SIMD) architecture, and Field Programmable Gate Arrays (FPGAs) offers a groundbreaking solution. Using the adaptability of FPGAs and SIMD parallelism, software testing processes can be dramatically accelerated. This study proposes a framework for parallel software testing using SIMD architecture in FPGA. To minimize the testing time of a generated software product, the proposed solution utilized hardware employed for process execution. The prototype of the proposed system achieved promising speedup up to 115X using FPGA slow mode, and 81X on average over Windows-based testing method.