The work is focused on developing the JTAG Verification IP capable of verifying the read-and-write operation on test data registers. JTAG interface VIPs focus on driving the interface using the correct protocol. However, they cannot account for the problem scenarios related to incorrect READ or WRITE on test data registers (TDRs) of the same length or read from read-only TDRs. Writing to incorrect TDR or READ from incorrect TDR may lead to incorrect chip functionality. All FPGAs, PLCs, and CPLDs use JTAG to access their programming functions. The incorrect connections to TDRs may lead to reading from the wrong TDR or writing into the wrong TDR, which, with interface JTAG VIP, will be undetected. Developed JTAG VIP solves the problem of verifying read-and-write operations by developing a UVM monitor and scoreboard that uses System Verilog to mimic the TAP state machine in the UVM scoreboard. The scoreboard keeps track of the current instruction value in the instruction register, the expected write value in the data register by observing the interface signal TDI, and the actual read value from the data register by observing the interface signal TDO. Further, the scoreboard fetches the actual write value and expected read value based on the current instruction from design using the UVM backdoor mechanism and compares the actual and expected values. The developed VIP verifies the successful read-and-write operations on the desired test data register, saving time and cost by detecting and eliminating bugs before the verification stage.