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Real-time digital audio processing plays a crucial role in modern electronic systems such as mobile devices, communication platforms, and multimedia applications. However, ensuring high-performance, low-latency processing under hardware constraints remains a significant challenge, particularly when integrating audio codec chips with FPGA platforms. This paper presents the design and implementation of a real-time digital audio processing system using FPGA technology and the WM8731 audio codec. Firstly, a robust I2C interface is developed to configure the WM8731 codec, ensuring accurate initialization and stable operation. Secondly, a serial-to-parallel adaptor (s2p_adaptor) is designed to convert I2S serial audio data into parallel format for digital processing, synchronized with bit and frame clocks. Finally, an 8-tap finite impulse response (FIR) filter is implemented using VHDL to enhance audio quality by suppressing high-frequency noise. All modules are synthesized in Quartus II and verified through ModelSim simulations and practical testing on an Altera DE1 development board. Timing diagrams based on the WM8731 datasheet and internal clock signals ensure precise synchronization. Experimental results demonstrate the effectiveness of the system, while final analysis highlights areas for further optimization and future improvements.

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FPGA-Based Real-Time FIR Filter for Digital Audio Processing

  • 会议论文

  • 发表日期：

    2026年

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  • Chenmu Ji,
  • Weibei Fan

摘要

Real-time digital audio processing plays a crucial role in modern electronic systems such as mobile devices, communication platforms, and multimedia applications. However, ensuring high-performance, low-latency processing under hardware constraints remains a significant challenge, particularly when integrating audio codec chips with FPGA platforms. This paper presents the design and implementation of a real-time digital audio processing system using FPGA technology and the WM8731 audio codec. Firstly, a robust I2C interface is developed to configure the WM8731 codec, ensuring accurate initialization and stable operation. Secondly, a serial-to-parallel adaptor (s2p_adaptor) is designed to convert I2S serial audio data into parallel format for digital processing, synchronized with bit and frame clocks. Finally, an 8-tap finite impulse response (FIR) filter is implemented using VHDL to enhance audio quality by suppressing high-frequency noise. All modules are synthesized in Quartus II and verified through ModelSim simulations and practical testing on an Altera DE1 development board. Timing diagrams based on the WM8731 datasheet and internal clock signals ensure precise synchronization. Experimental results demonstrate the effectiveness of the system, while final analysis highlights areas for further optimization and future improvements.