This work presents new hardware architectures for AES-128 encryption tailored to resource-constrained IoT devices. We propose 32-bit and 64-bit round-based designs that significantly increase throughput while maintaining an efficient area–performance balance. Each datapath includes an independent key schedule module capable of generating multiple round key bytes per cycle in parallel with encryption, eliminating key-setup latency. Both architectures use the lightweight S-box [11] and are synthesized in STM 65 nm CMOS technology for fair comparison with the 16-bit baseline in [2]. The proposed 32-bit and 64-bit designs reduce encryption latency to 44 and 22 cycles per 128-bit block and increase throughput from 734 Mbps to 1.512 Gbps and 2.950 Gbps, corresponding to improvements of 106% and 301.9%, respectively. These gains are achieved with area overheads of 29.1% and 84.4%. Energy consumption per block decreases from 7.62 nJ to 4.69 nJ and 3.37 nJ at 10 MHz. Both architectures also improve throughput-per-area, achieving 1.60 \(\times \) and 2.18 \(\times \) higher efficiency than the baseline. Compared to designs in [13], they achieve lower latency with fewer S-boxes, resulting in smaller area and higher throughput. These features make the architectures well suited for low-latency, energy-efficient AES implementations in IoT hardware.