Many True Random Number Generators (TRNGs) extract randomness from a jittered clock generated by an oscillator either by directly sampling this clock (in sampling mode) or by counting the number of samples equal to one during a reference interval (in counting mode). This architectural choice has a decisive impact on the statistical quality of the output bit stream. Previous works suggest that counting provides an advantage over sampling mode, arguing that jitter accumulation over many oscillator periods yields higher entropy per output bit. The aim of this work is to study both methods more closely using a unified framework of standard random tests. We analyze experimental data acquired from the two TRNG configurations implemented in a Field Programmable Gate Array (FPGA) in self-timed rings (STR). The results show that the sampling method produces higher correlation values that are consistent with other tests: Markov chains, run length, balance, etc. Additionally, we provide results over free running oscillator-based TRNG architectures and we derive experimental limits of the parameters of the two TRNG configurations.