The increased growth of data-intensive applications like machine learning, artificial intelligence, and edge computing has revealed the limitations of conventional von Neumann architecture, mainly the memory bottleneck resulting from constant data transfers. SRAM-based Compute-in-Memory (CIM) architectures help to address this issue by performing computations directly within the memory arrays, which reduces latency and energy consumption. The current work presents a literature review of SRAM-based Compute-in-Memory (CIM) architectures, with a main focus on error-tolerant, energy-efficient designs. Based on this review, a 10T SRAM that contains logic-and-dummy-cells is proposed here. Here, the main aim is to increase computational property and CIM system’s error tolerance. The most significant research papers are reviewed here which points out the numerous properties of the design of SRAM cells from multi-transistor designs to traditional 6T-SRAM designs. From the reviewed papers, a clear image of the improvement is reflected. Among the available memory technologies, SRAM is efficient because the main features of this memory technology is speed, compatibility and adaptability. This paper marks the importance of reliability in low voltage and radiation prone environments. Here, the proposed 10T SRAM architecture improves robustness without energy loss by integrating conditional logic and dummy cell shielding. This makes the technology suitable for AI-accelerators, IoT edge devices and other applications in aerospace and defense. Overall, this particular work highlights SRAM-based CIM as a potential solution for high performance platforms.