As computing needs are expanding, scaling up the general-purpose computing resources is limited by energy consumption and efficiency. Coarse-Grained Reconfigurable Arrays (CGRAs) are a solution to that challenge: they are versatile digital architectures, capable of achieving near-ASIC level of energy efficiency without sacrificing reconfigurability. However, CGRAs are limited to the instructions they were built with. Unsupported operations must be emulated, which severely impacts performance. To preserve CGRAs inherent features while enabling higher reprogrammability, we propose MultiGRA: an architecture template that expands the fixed CGRA’s instruction set by including embedded FPGA fabrics (eFPGA) inside the CGRA as finely reconfigurable zones. The eFPGA areas are capable of implementing application-specific operators, specialized at compilation time. This approach avoids overprovisioning computing resources, since the architecture can be freely retargeted. We investigate two of the many integration possibilities of eFPGAs in CGRAs with the respective gains. Examples of post-synthesis ASIC area measurements are provided to show integration feasibility. In a case study comparing CGRAs and MultiGRAs, MultiGRAs show up to 40% improvement in execution time.