This work presents the design and optimization of a high-performance 8 \(\times \) 8 multiplier for accelerating deep neural network (DNN) computations on FPGAs. The proposed design initially optimizes an existing architecture to achieve higher speed and improved hardware efficiency, followed by the application of approximate computing techniques to further reduce power consumption and area with minimal accuracy loss. Experimental results targeting the XCZU9EG-2FFVB1156 FPGA demonstrate that the precise Optimized BitParticle (OBP) achieves a 33.3% improvement in instructions per cycle (IPC) compared with the baseline architecture. Furthermore, the proposed multiplier is evaluated on lightweight DNN models and standard datasets, showing that the approximate variant provides substantial gains in energy and resource efficiency with negligible impact on inference accuracy. The Approximate-Optimized BitParticle (AOBP) reduces the accuracy loss to 3.34% on LeNet–MNIST and 6.06% on GeNet–MNIST, outperforming the baseline and achieving comparable or better performance than PAM1/PAM2 on SVHN, demonstrating its suitability for energy-efficient AI hardware.