With the rapid development of network and information technology, the demand for high-performance cryptosystems is growing, and cryptographic algorithm acceleration systems have become a hot research topic nowadays. As one of the cryptographic algorithm implementation methods, reconfigurable computing systems can take into account the advantages of general-purpose processors and special integrated circuits, thus becoming the main research direction of cryptographic implementation nowadays. At present, a large number of teams have explored the hardware technology of reconfigurable-based cryptographic algorithm acceleration systems, but they have only explored it from the perspective of engineering realization and lacked the method of designing at the system level. To address the above problems, this paper summarizes the existing hardware acceleration design and optimization techniques for reconfigurable cryptosystems into three categories: system-level, component-level, and configuration-level. At the same time, it analyzes the hardware structure and design flow based on the classification and points out the existing problems in the current research. Finally, the future development direction of hardware-accelerated design and optimization techniques for reconfigurable cryptosystems is discussed to provide new perspectives.