Scholarlink

This research work presents the design and analysis of a low-power Phase-Locked Loop (PLL) implemented using 90 nm CMOS technology. The PLL architecture has five main parts: Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LPF), Voltage-Controlled Oscillator (VCO), and Frequency Divider (FD). Each of these blocks was implemented in a manner to maintain a low power and stable frequency output. The VCO implemented a center frequency of 1.472 GHz and the total PLL was designed to use around 45.5 µW of power. Simulation results verified phase locking, stable frequency generation, and low power operation. The results suggest that the 90 nm CMOS technology presents a promising platform for the development of compact, low-power, on-chip frequency synthesizers suitable for future applications.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Low-Power CMOS Phase-Locked Loop Design and Performance Evaluation in GPDK 90nm Technology

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Vinay K. Kolur,
  • Jayalaxmi Gonal,
  • Rashmi Nimbaragi

摘要

This research work presents the design and analysis of a low-power Phase-Locked Loop (PLL) implemented using 90 nm CMOS technology. The PLL architecture has five main parts: Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LPF), Voltage-Controlled Oscillator (VCO), and Frequency Divider (FD). Each of these blocks was implemented in a manner to maintain a low power and stable frequency output. The VCO implemented a center frequency of 1.472 GHz and the total PLL was designed to use around 45.5 µW of power. Simulation results verified phase locking, stable frequency generation, and low power operation. The results suggest that the 90 nm CMOS technology presents a promising platform for the development of compact, low-power, on-chip frequency synthesizers suitable for future applications.