In today’s world of digital technology, the need for faster and power-efficient arithmetic units is essential, especially in low-power and high-performance systems like mobile devices, embedded processors, and signal processing units. Traditional adders, such as the Ripple Carry Adder (RCA) and the Carry Lookahead Adder (CLA), have limitations in speed, power use, and silicon area, which worsen as circuit complexity increases. The Brent-Kung Adder (BKA), a parallel prefix adder, provides better performance by lowering logic levels and fan-out. However, its CMOS implementation results in a higher transistor count, increased dynamic power, and larger layout area, making it unsuitable for power-sensitive applications. To address these issues, this project introduces a Brent-Kung Adder designed with the Gate Diffusion Input (GDI) technique, a low-power approach that reduces transistor count and improves power and area efficiency compared to CMOS. The GDI-based BKA is designed and simulated using the Cadence Virtuoso EDA tool in 90 nm technology. Key parameters such as propagation delay, power consumption, and layout area are evaluated. Simulation results show that the GDI implementation significantly enhances speed and power efficiency, making it ideal for modern VLSI systems that need compact and energy-efficient arithmetic circuits.