RISC-V is becoming increasingly significant due to its numerous applications in embedded processors, edge computing, automotive, and custom processors. In the era of modern computing, where multitasking and real-time operations are the norm, interrupt handling is crucial for maintaining system responsiveness and managing various tasks concurrently. However, the existing default interrupt controller is still lagging in areas such as prioritization. This paper discusses the design and implementation of the Core Local Interrupt Controller (CLIC) to handle interrupts effectively using Cadence Xcelium software for integration. Additionally, the generation of interrupts based on priority is addressed. Initially, the interrupts are detected, and the prioritized signal is computed. Various test cases are evaluated for testing purposes. Furthermore, this paper provides a detailed analysis of CLIC’s functionalities and its superiority over existing interrupt controllers, particularly the Core Local Interruptor (CLINT), shedding light on the current challenges, future research directions, and emerging trends in interrupt controller design, contributing to the optimization of RISC-V architecture, especially in real-time systems. The paper describes a hierarchical Verilog implementation of an interrupt resolver system based on priorities, which provides useful experience on how interrupt handling systems can be implemented on FPGA-based RISC-V processors.