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This Chapter discusses the different approaches proposed over the years to automate the sizing task of analog integrated circuits (ICs). The traditional approaches of knowledge and equation-based solutions have been left behind for industry and academically accepted simulation-based optimizations. However, due to the time and computational cost of such circuit simulations, machine learning (ML) algorithms have been leveraged to help such techniques. The recent advances in ML and deep learning (DL) techniques have been offering new alternatives to the design automation of ICs not only on the mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE Trans Comput Aided Des Integr Circuits Syst 22:198–212, 2003; Alpaydin et al in IEEE Trans Evol Comput 7(3):240–252, 2003; Liu et al in Proceedings 2002 design automation conference, pp 437–442, 2002), i.e., replacing the simulator, but also on a broader set of design problems (Mina et al in Electron MDPI 11(3):435, 2022; Martins and Lourenço in IEEE Access 11:35965–35983, 2023; Wang et al in Proceedings of the IEEE international symposium on radio-frequency integration technology, pp 1–3, 2024; Maji et al in Proceedings of the 29th Asia and South Pacific design automation conference, pp 657–664, 2024; Martins in Microelectron MDPI 1(1, 2), 2025). These include applications such as the inverse sizing problem, i.e., the mapping from specifications to the devices’ sizes (Azevedo et al in Expert Syst Appl 290:128,414, 2025; Eid et al in AEU Int J Electron Commun 195:155,767, 2025), layout generation (Zhu et al in Proceedings of the IEEE/ACM international conference on computer-aided design, pp 1–8, 2019; Gusmão et al in Expert Syst Appl 207:117954, 2022; Gusmão et al in Appl Soft Comput 115:108188, 2022; Gusmão et al in ACM/IEEE design automation conference, pp 1360–1361, 2021), fault testing (Andraud et al in IEEE Trans Circuits Syst I Regul Pap 63:2022–2035, 2016), and so on. Therefore, other ML-based solutions for analog IC sizing beyond traditional simulation-based have also been proposed, and are here explored and analyzed, with a particular focus on reinforcement learning (RL) and transfer learning-based training. Furthermore, incorporating process, voltage, and temperature (PVT) corners into analog IC design is more critical than ever, as circuits are increasingly required to operate under the most adverse conditions. However, this topic has received limited attention in recent academic research, with only a handful of works reflecting its growing importance (Passos et al in Int VLSI 63:351–361, 2018; Mendes et al in IEEE Access 9:70353–70368, 2021).

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  • 章节

  • 发表日期：

    2026年

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  • Pedro Alberto Oliveira Paiva,
  • José Pedro Ponte Mota da Costa,
  • Filipe Parrado de Azevedo,
  • Ricardo Miguel Ferreira Martins

摘要

This Chapter discusses the different approaches proposed over the years to automate the sizing task of analog integrated circuits (ICs). The traditional approaches of knowledge and equation-based solutions have been left behind for industry and academically accepted simulation-based optimizations. However, due to the time and computational cost of such circuit simulations, machine learning (ML) algorithms have been leveraged to help such techniques. The recent advances in ML and deep learning (DL) techniques have been offering new alternatives to the design automation of ICs not only on the mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE Trans Comput Aided Des Integr Circuits Syst 22:198–212, 2003; Alpaydin et al in IEEE Trans Evol Comput 7(3):240–252, 2003; Liu et al in Proceedings 2002 design automation conference, pp 437–442, 2002), i.e., replacing the simulator, but also on a broader set of design problems (Mina et al in Electron MDPI 11(3):435, 2022; Martins and Lourenço in IEEE Access 11:35965–35983, 2023; Wang et al in Proceedings of the IEEE international symposium on radio-frequency integration technology, pp 1–3, 2024; Maji et al in Proceedings of the 29th Asia and South Pacific design automation conference, pp 657–664, 2024; Martins in Microelectron MDPI 1(1, 2), 2025). These include applications such as the inverse sizing problem, i.e., the mapping from specifications to the devices’ sizes (Azevedo et al in Expert Syst Appl 290:128,414, 2025; Eid et al in AEU Int J Electron Commun 195:155,767, 2025), layout generation (Zhu et al in Proceedings of the IEEE/ACM international conference on computer-aided design, pp 1–8, 2019; Gusmão et al in Expert Syst Appl 207:117954, 2022; Gusmão et al in Appl Soft Comput 115:108188, 2022; Gusmão et al in ACM/IEEE design automation conference, pp 1360–1361, 2021), fault testing (Andraud et al in IEEE Trans Circuits Syst I Regul Pap 63:2022–2035, 2016), and so on. Therefore, other ML-based solutions for analog IC sizing beyond traditional simulation-based have also been proposed, and are here explored and analyzed, with a particular focus on reinforcement learning (RL) and transfer learning-based training. Furthermore, incorporating process, voltage, and temperature (PVT) corners into analog IC design is more critical than ever, as circuits are increasingly required to operate under the most adverse conditions. However, this topic has received limited attention in recent academic research, with only a handful of works reflecting its growing importance (Passos et al in Int VLSI 63:351–361, 2018; Mendes et al in IEEE Access 9:70353–70368, 2021).