In this paper, we attempt an analysis of the cache controller implementation in an open-source multi-core implementation of RISC-V. In particular, we examine the Boston RISC-V (BRISC-V) codebase with a special focus to the L1 cache controller implementation. We adopt a targeted test generation approach to verify the load store functionalities, and track the flow of data through the controller to examine its compliance with the expected behavior. The L1 cache controller in BRISC-V is unified, in the sense, that a single controller handles both the Instruction and Data cache. In a multi-core setup, considering that coherence management is involved only for the data cache, we propose a split controller design, wherein the unified controller is split into two separate ones, one for handling the data cache and the other for handling the instruction cache. This helps us work with separate instruction and data addresses in the fetch and memory access stages. We verify through experiments that the split controller achieves the same functionality as the unified one for all operations.